technical data iw4043b quad 3-state r/s latches high-voltage silicon-gate cmos ordering information IW4043BN plastic iw4043bd soic t a = -55 to 125 c for all packages the iw4043b types are quad cross-coupled 3-state cmos nor latces. each latch has a separate q output and individual set and reset inputs. the q outputs are controlled by a common enable input. a logic ?1? or high on the enable input connects the latch states to the q outputs. a logic ?0? or low on the enable input disconnects the latch states from the q outputs, resulting in an open circuit condition on the q outputs. the open circuit feature allows common busing of the outputs. ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package-temperature range; 100 na at 18 v and 25 c ? noise margin (over full p ackage temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply pin assignment function table inputs outputs s r oe q x x l high impedance l l h no change l h h l h l h h h h h h x = don?t care logic diagram pin 13 = no connection pin 16=v cc pin 8= gnd rev. 00
iw4043b rev. 00 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the reco mmended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard ag ainst damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of an y voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
iw4043b rev. 00 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c 25 c 125 c unit v ih minimum high-level input voltage v out = 0.5 v or v cc - 0.5v v out = 1.0 v or v cc - 1.0 v v out = 1.5 v or v cc - 1.5v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low - level input voltage v out = 0.5 v or v cc - 0.5v v out = 1.0 v or v cc - 1.0 v v out = 1.5 v or v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i oz maximum three state leakage current output in high-impedance state v in = gnd or v cc v out = gnd or v cc 18 0.4 0.4 12.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 1 2 4 20 1 2 4 20 30 60 120 600 a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 -2 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma
iw4043b ac electrical characteristics (c l =50pf, r l =200k , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c 25 c 125 c unit t phl , t plh maximum propagation delay, set or reset to q (figure 1) 5.0 10 15 300 140 100 300 140 100 600 280 200 ns t phz , t pzh maximum propagation delay, output enable to q (figures 2,4) 5.0 10 15 230 110 80 230 110 80 460 220 160 ns t plz , t pzl maximum propagation delay, output enable to q (figures 2,4) 5.0 10 15 180 100 70 180 100 70 360 200 140 ns t thl , t tlh maximum output transition time, any output (figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance - 7.5 pf timing requirements (c l =50pf, r l =200 k , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v unit -55 c 25 c 125 c t w minimum pulse width, set or reset (figure 3) 5.0 10 15 160 80 40 160 80 40 320 160 80 ns figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms rev. 00
iw4043b test in in a t phz v cc gnd gnd t plz gnd v cc v cc t pzh v cc gnd gnd t pzl gnd v cc v cc figure 4. test circuit expanded logic diagram ( 1/4 of the device) rev. 00
iw4043b n suffix plastic (ms - 001bb) notes: l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 16 8 9 dimensions, mm symbol min max a 18.67 19.69 b 6.10 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 j 0 10 k 2.92 3.81 l 7.62 8.26 m 0.20 0.36 n 1. imensions ?a?, ?b? do not include mold flash or protrusions. maximum mold flash or protrusions 0.25 mm (0.010) per side. 0.38 rev. 00 d suffix soic (ms - 012ac) a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 16 8 9 dimensions, mm symbol . min max a 9.80 10.0 b 3.80 4.00 c 1.35 1.75 d 0.33 0.51 f 0.40 1.27 g 1.27 h 5.72 j 0 8 k 0.10 0.25 notes: m 0.19 0.25 1.dimensions a and b do not include mold flash or protrusion. p 5.80 6.20 2.maximum mold flash or protrusion 0.15 mm (0.006) per side for a, for b - 0.25 mm (0.010) per side. r 0.25 0.50
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